A. Field of the Invention
The present invention relates generally to the field of wireless communications. More particularly, the present invention relates to RF receiver mismatch calibration.
B. Background
Recently, the demand for wireless communication has grown significantly, such as for wireless local area networks (LAN), home wireless control systems and wireless multimedia centers. Along with this growth in demand, there has been an increased interest in more bandwidth, more powerful and cheaper chips. For example, the maximum 11 Mb/s bandwidth offered by the IEEE 802.11b standard cannot satisfy the growing demand on higher bandwidth. Rather, 54 Mb/s rate offered by the 802.11g or 11a standards is preferred. To transmit in this bandwidth with just a 20 MHz wide channel, more advanced modulation methods other than simple binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) should be adopted. In the IEEE 802.11a/g wide local area network (WLAN) system, the data is modulated with BPSK, QPSK, 16QAM (quadrature amplitude modulation) or 64QAM, and is further mapped onto 52 subcarriers of an orthogonal-frequency-division-multiplexed (OFDM) signal.
To take advantage of the high bandwidth, the OFDM-based wireless system and other radio systems with sophisticated modulation methods pose significant implementation challenges. These challenges include requiring low in-band phase noise, high linearity and accurate quadrature matching inside the RF chip. Among them, quadrature matching is the most complicated issue since it arises from the device mismatch and since it varies from chip to chip. Also the requirement for the mismatch is typically very tight. For example, in order to meet the receiver Error Vector Magnitude (EVM) specification for 54 Mb/s mode in a WLAN system with a 3-dB implementation margin, which indicates the quality of the digital modulated signals, system simulation shows that an I/Q mismatch of less than 1°/0.2 dB is required.
An RF receiver used in a wireless system performs RF signal de-modulation, down-conversion of the signal, adjacent interference rejection and baseband signal amplification. Compared with an unchanged transmitter implementation, there are many parameters to be addressed in an RF receiver realization. This is because there are more considerations for a receiver design, such as noise, linearity, interference rejection and band selection. Although the homodyne (direct conversion) receiver architecture has been in use for many years, the heterodyne receiver architecture is the first to be widely used. The heterodyne receiver architecture utilizes a mixer to translate a filtered channel centered at a high frequency to a much lower intermediate frequency, so as to relax the required quality of the channel select filter. Since the local oscillation (LO) frequency of the mixer is different from the input RF frequency, it has to deal with an image problem that occurs during the receiving process. Image rejection filter and other topologies such as dual-IF architecture are exploited to improve the reception. However, the mismatch between the inphase and quadrature (I/Q) branches degrades the receiver performance if the I/Q separation occurs inside the RF chip. A dual IF architecture has the advantage of alleviating this problem because the I/Q separation occurs at a lower frequency path which tends to have smaller mismatch. This is especially true for the phase mismatch as compared with the separation occurring at a higher frequency path.
If the down conversion mixer of the RF receiver converts the high frequency signal directly to the zero intermediate frequency, the RF receiver is called a homodyne wireless receiver, which is also referred to as a “direct conversion” or “zero-IF” receiver. It avoids the image problem in the heterodyne receiver architecture, but it introduces DC offset voltage during receiving, which is generated by the self-mixing between the LO signals and the LO leakage from both the receiver and the transmitter. Moreover, because the I/Q separation in the homodyne receiver architecture occurs at an RF frequency, it suffers from a larger phase mismatch.
The trade-offs governing the utilization of image-reject filters in the heterodyne receiver architecture have motivated RF designers to seek other techniques for suppressing the images. Hartley architectures and Weaver architecture are two such examples. Since these architectures utilize the signals in quadrature branches to do the image rejection, they are more prone to mismatch as compared to the homodyne and the heterodyne receiver architectures. Also, digital IF receivers that perform I/Q separation in the digital domain remove the mismatch in the RF receiver but increase the complexity for the digital processing circuit.
FIGS. 1 to 3 show the above conventional cases. FIG. 1 shows an RF receiver in which the quadrature signals separation occurs at a high frequency domain. This conversion method is adopted by one step direct conversion receiver and image rejection receiver such as the Weaver or the Hartley type. The architecture shown in FIG. 1 is the most sensitive to quadrature mismatches. As shown in FIG. 1, an input RF signal fLO+fs (whereby fs is an input signal that is modulated with a carrier frequency fLO by an RF transmitter, not shown) is received by a receiver antenna 110, and provided to a low noise amplifier (LNA) 120. The output of the LNA 120 is provided to an I/Q mixer 125, whereby the input RF signal is mixed with a local oscillator signal LO output by a local oscillator 127, to provide baseband I and Q signals that are filtered by a filter 130 in order to remove the adjacent interference. Accordingly, the input signal fs is obtained, and is provided to a variable gain amplifier VGA 140, whereby the output of the VGA 140 corresponds to the demodulated RF signal. The demodulated RF signal is then provided to a digital baseband circuit, for additional processing (e.g., digital signal processing).
FIG. 2 shows an RF receiver 200 in which the quadrature signals separation occurs at a relatively lower frequency as compared to the RF receiver 100 of FIG. 1. The RF receiver 200 of FIG. 2 has a lesser quadrature mismatch problem as compared to the RF receiver 100 of FIG. 1, whereby the RF receiver 200 of FIG. 2 is used by either a dual IF direct conversion receiver system or by a heterodyne receiver system. As shown in FIG. 2, an input RF signal fLO1+fLO2+fs (whereby fs is an input signal that is modulated by carriers fLO1 and fLO2 by an RF transmitter, not shown) is received by a receiver antenna 210, and provided to an LNA 220. The output of the LNA 220 is provided to a first mixer 225, whereby the input RF signal is mixed with a first local oscillator signal LO1 output by a first local oscillator 227, to provide an intermediate frequency (IF) signal fLO2+fs (and its sideband image). The sideband image is filtered by off-chip filter 230, and the intermediate frequency signal is then provided to a second mixer (I/Q mixer) 240, whereby I/Q separation occurs at IF. The second mixer 240 mixes the IF signal with a second local oscillator signal LO2 output by a second local oscillator 242, to provide a baseband signal (and its sideband image). A filter 250 filters the adjacent inteference, to thereby provide the input signal fs to a VGA 260, whereby the output of the VGA 260 corresponds to the demodulated RF signal. The demodulated RF signal is then provided to a digital baseband unit (not shown), for further processing of the received data (e.g., digital signal processing).
FIG. 3 shows an RF receiver 300 in which the quadrature signals separation occurs in a digital base band circuit after the RF receiver and after quantization. The approach of FIG. 3 is free of quadrature mismatch (also referred to herein simply as “mismatch”). The difference between the RF receiver 300 and the RF receiver 200 of FIG. 2 is that I/Q separation occurs at the output of the VGA 360 in FIG. 3 (digital I/Q separation), whereby the I/Q separation occurs at the output of the second mixer 240 in FIG. 2 (analog I/Q separation). In the RF receiver 300 of FIG. 3, the second mixer 340 is not an I/Q mixer.
Different calibration methods have been utilized to perform calibration for conventional RF transceivers. Some of calibration methods use a local transmitter, which has already been calibrated, to send the test vectors to the RF receiver and compute the mismatch compensation factor through a digital signal processing (DSP) machine in a digital baseband circuit of the RF transceiver. This is called “local calibration” and typically is performed during a system power up process or during an idle time (e.g., between times when data is sent from an RF transmitter to an RF receiver). Compensation factors can be applied to the RF transceiver if there is mismatch compensation detected within an RF chip of the RF transceiver, or they can be directly applied after analog-to-digital conversion (ADC) in the digital domain.
In another type of calibration method, a remote transmitter adds particular information (e.g., predetermined data) in the transmitting sequence to aid in the receiver calibration at the RF receiver. This type of calibration can be done in real time, whereby it results in decreased channel efficiency (due to the extra coding spent performing calibration). This calibration method is typically referred to as “remote calibration”.
In terms of mismatch detection and calibration locations, the conventional calibration methods can be categorized into two subtypes. In a first subtype, both the mismatch detection and the calibration are done by a digital baseband circuit of the RF transceiver. As shown in FIG. 4, a digital baseband circuit 410 transmits a pilot sequence to an RF chip (RF transceiver) 420, whereby the pilot sequence is modulated into a high frequency signal by a transmitter (included in the digital baseband circuit 410). The RF chip 420 receives and transmits signals over-the-air to/from a remote RF transceiver, via RF antenna 450. During calibration, the RF chip 420 couples the transmitter output of the digital baseband circuit 410 to its receiver input (by way of an RF switch on chip, not shown). In that way, the local digital baseband can receive the demodulated signal output from the RF chip 420 (by way of an A/D converter 440) at the same time it is providing calibration data to the RF chip 420 (by way of a local loop). An error signal output by the digital baseband circuit 410 is subtracted from the A/D output of the A/D converter 440 in the local loop (which corresponds to a digital representation of the original calibration signal), to thereby provide a correction signal to the digital baseband circuit 410 (which is used to calibrate the RF chip 420).
A powerful DSP machine within the digital baseband circuit 410 is required to calculate the phase and amplitude mismatch of the RF link and generate the “error” signals to calibrate the RF link. Although the calibration is easy to control in the digital domain, it imposes several disadvantages: 1) The DSP machine is complicated and the computation takes a long time to get the desired accuracy; 2) it cannot work without an RF transmitter; 3) the mismatch introduced by the transmitter has to be considered since the transmitter mismatch cannot be completely cancelled; 4) the hardware mismatch is intact and the performance degradation introduced by those mismatches, such as second order inter-modulation, are still there; and 5) the extra connection between the transmitter and the receiver of the RF chip 420 complicates the design.
FIG. 5 shows the second subtype for performing calibration, whereby this system uses a digital baseband circuit to detect the signal mismatch while the circuits inside the RF chip (RF transceiver) 520 perform the calibration (based on information provided by the digital baseband circuit 510). Like the system of FIG. 4, a local loop that includes a D/A converter 530 and an A/D converter 540 is used to provide calibration data to and from the digital baseband circuit 510 and the RF chip 520. The RF chip 520 receives and transmits signals over-the-air to/from a remote RF transceiver, via RF antenna 550 during normal application. During calibration, the RF chip 520 receives the signal sent by itself through an on chip RF switch (not shown). Note that the system of FIG. 5 utilizes a calibration command that is output from the digital baseband circuit 510 directly to the RF chip 520, which is different from the way calibration is performed in the system of FIG. 4.
The disadvantages of this second subtype of calibration are: 1) complicated DSP machine and required substantial computational power; 2) dependence on RF transmitter; 3) introduction of the transmitter mismatch since the transmitter mismatch cannot be completely calibrated out; and 4) extra connection required between the transmitter and the receiver inside the RF chip complicates the design.
Since the mismatch detection or the calibration are done by the baseband digital circuit for both the first and the second calibration subtypes discussed above, even if the mismatch is calibrated out for one single frequency and under particular test vectors; their effects will still show in other frequency bands or with different input signals. To improve the existing calibration methods, different compensation factors are applied to each frequency band and with various input signals, which exploit extra memory such as a random access memory (RAM) or an electrically erasable programmable read only memory (EEPROM), in order to store a compensation look-up table. Also, the calibration period becomes longer accordingly because the mismatches should preferably be calculated under different conditions.
Among all of above conventional calibration methods described above, the phase mismatch and amplitude mismatch are calibrated together, whereby it is difficult to differentiate between them. Actually, in an RF receiver, the phase mismatch is more serious than the amplitude mismatch. The phase mismatch is contributed by the local oscillation (LO) signals and down-conversion mixer and is difficult to minimize. This is because the small device mismatch is converted into a relatively large phase offset in high frequency and the circuit working in the RF domain cannot tolerate too much parasitic capacitance which limits the application of layout optimization method such as crossing or interdigitation. Monte Carlo simulation shows that the LO signals could easily have 1.5 degree phase mismatch at 5 GHz, while the down-conversion mixer contributes 1 degree. Thus, there is a total of at least 2.5 degrees phase mismatch.